1. Field of the Invention
The present invention relates to a flash memory capable of changing a plurality of bank configurations, and in particular to a flash memory which has a common memory circuit configuration, and which can change it into a 2-bank configuration or a 4-bank configuration by setting a product data.
2. Description of the Related Arts
A flash memory has a nonvolatile memory cell, and is erased and programmed in sector unit having a plurality of memory cells. An operation mode of the flash memory has a readout mode of reading stored data out, an erase mode of writing data xe2x80x9c1xe2x80x9d in all the memory cells in selected sectors, and a program mode of writing data xe2x80x9c0xe2x80x9d in the selected memory cell. The flash memory responds to a command write signal to be set to the erase mode or program mode.
As the flash memory is a nonvolatile memory which can hold memory data even in a state that a power supply is off, in many cases, it is utilized as a semiconductor memory which records a boot program which is accessed initially when the power supply is started. Accompanied by the condition, the flash memory is frequently configured by a bank having a boot sector which is accessed when the power supply is started, and a bank having the other normal sectors. In such a case, a bank configuration in response to a user""s conveniences is demanded from a product that a capacitance of the bank having the boot sector is smaller than that of the other banks to a product that a capacitance of the former is equivalent to the latter.
Furthermore, in characteristic points of the flash memory, in the program mode or erase mode which is executed in response to the command write signal, a stress applying step of applying a fixed program pulse or erase pulse to the memory cell having a floating gate and a verifying step of checking a change of a threshold voltage of the memory cell after the stress pulses are repeatedly applied in a plurality of times. For this reason, the flash memory prohibits readout operations with respect to the bank during program or erase operations. In other words, when a sector in a certain bank is under the program or erase operations, even if the readout operation is for a memory cell of another sector in the bank, the readout operations are prohibited. Moreover, as the program or erase operations demand a longer time than the readout operations, once the program or erase operations are started with respect to a certain bank, a readable memory region is lessened so that the readout operations are limited to some extent. In other words, in the case where the flash memory has a 2-bank configuration, while one bank is under the program or erase operations, the other bank can carry out the readout operations, but such the one bank cannot carry them out.
Furthermore, in characteristic points of the flash memory, a top boot that an address of the bank having the boot sector is allocated to a most significant address and a bottom boot that the address is allocated to a least significant address are present. The top boot flash memory differs from the bottom boot flash memory in that, when the flash memory is mounted in a system, an access to the boot program in the flash memory is made according to the most significant address or the least significant address.
A conventional flash memory has generically a 2-bank configuration, but a product of a 4-bank configuration is being lately demanded in order to reduce a constraint of the readout operations. In other words, it is possible to decrease a capacitance of the memory which cannot be accessed due to under the program or erase operations, by increasing the number of banks.
Furthermore, even if having the 2-bank configuration, a plurality of products having various sizes in the capacitance of the bank having the boot sector as compared with the other banks are demanded.
However, it is not efficient either preferable in views of a production control to design and manufacture a plurality of the flash memories corresponding to the large number of products.
It is therefore an object of the present invention to provide the flash memory which is a common memory circuit, and which can comply with a desirable product by setting product data.
It is another object of the present invention to provide the flash memory which has different bank configurations, and which can cope with a plurality of products in which addresses allocated to the plurality of banks are different in order, respectively.
In order to attain the aforementioned objects, according to one aspect of the present invention, the flash memory comprises a memory region is divided into a plurality of real banks, wherein from among the plurality of products which consists of combinations of virtual banks having at least one real bank; and a combination of the top boot in which the most significant address is allocated to the boot bank having the boot sector and the bottom boot in which the least significant address is allocated to the boot bank, product information data are set in a product information record section, whereby any product can be configured.
According to the aforementioned aspect, in a preferred embodiment, the memory region in the flash memory has the plurality of real banks which have a memory cell array, a word driver and a column selection circuit, respectively. A bank busy detection circuits are provided in each real bank. The bank busy detection circuit records whether or not the corresponding real bank is under the program or erase operations, and generates a readout enabling signal which in response to a bank selecting signal at the time of readout, prohibits a readout if under the program or erase operations and enables to read out if not under the program or erase operations. The bank busy detection circuit, according to whether or not the other real banks belonging to the virtual bank set by the product data are under the program or erase operations, set the readout enabling signal into a prohibition or enable state.
An another aspect of the present invention provides a nonvolatile memory which can modify a configuration of a virtual bank having at least one real bank, comprising a plurality of real banks having a plurality of memory cells, respectively; a product information memory for storing product information data having the virtual bank configuration; an address transforming section for converting an address to be supplied into an internal address according to the product information data; and a bank busy detection circuit which is provided in each of the real banks, and generates a program/erase state signal designating whether or not the corresponding real bank is under the program or erase operations, and in response to a real bank selecting signal at the time of a readout, generates a readout enabling signal for instructing an enabling or prohibition of a readout of such the corresponding real bank in accordance with the program/erase state signal of the real bank belonging to the same virtual bank, wherein the real bank belonging to the virtual bank is configured to be modified in accordance with the product information data, and the bank busy detection circuit generates the readout enabling signal of prohibiting the readout when any one of the program/erase state signals of the real bank belonging to the virtual bank established according to the product information data is in a program or erase operations state.
Furthermore, in the preferred embodiment, a bank decoder is provided which decodes an internal address which is an address for selecting the real bank, and is formed by the address transforming circuit, and which generates a real bank selecting signal. The real bank selecting signal generated by the bank decoder is supplied to the bank busy detection circuit, which generates the readout enabling signal according to whether or not the real bank belonging to the same virtual bank is under the program or erase operations, according to the real bank selecting signal.
According to the above aspect, in the preferred embodiment, the flash memory comprises the address transforming circuit which converts a supplied address into the internal address, and such the address transforming circuit converts the address of the real bank corresponding to the boot bank into the most significant or least significant, according to the top boot or bottom boot set by the product data.
Furthermore, in the preferred embodiment, the product information record section has a nonvolatile memory cell, and in which the product information data is writable in the nonvolatile memory cell. Thus, with respect to the common memory circuit, the product information data is written into the nonvolatile memory cell in the product information record section after an end of a manufacturing process, so that it is possible to set as a desirable product from among the plurality of products. Accordingly, it is possible to facilitate the production control.